The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of the IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of designing ICs and, for these advances to be realized, similar developments in IC design methods are needed.
For example, as the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of various IC design methods that utilize optical proximity correction (OPC) and enforcement of mask rule check (MRC). During the IC design, the design pattern is adjusted to meet the specification of mask-making and the mask manufacturing capability which is determined by the MRC. However, the enforcement of MRC leads to erosion and reduction of the OPC simulated contour hitting the target. Accordingly, although existing IC design methods have been generally adequate for their intended purpose, they have not been entirely satisfactory in all respects.